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ddr3 sdram udimm mt4jtf6464az C 512mb mt4jtf12864az C 1gb features ? ddr3 functionality and operations supported as de- fined in the component data sheet ? 240-pin, unbuffered dual in-line memory module (udimm) ? fast data transfer rates: pc3-12800, pc3-10600, pc3-8500, or pc3-6400 ? 512 (128 meg x 64), 1gb (128 meg x 64) ? v dd = v ddq = +1.5v 0.075v ? v ddspd = +3.0v to +3.6v ? reset pin for improved system stability ? nominal and dynamic on-die termination (odt) for data, strobe, and mask signals ? single rank ? fixed burst chop (bc) of 4 and burst length (bl) of 8 via the mode register set (mrs) ? adjustable data-output drive strength ? serial presence-detect (spd) eeprom ? gold edge contacts ? halogen-free ? fly-by topology ? terminated control, command, and address bus figure 1: 240-pin udimm (mo-269 r/c c) module height: 30.0mm (1.181in) options marking ? operating temperature 1 C commercial (0c t a +70c) none ? package C 240-pin dimm (halogen-free) z ? frequency/cas latency C 1.25ns @ cl = 11 (ddr3-1600) -1g6 C 1.5ns @ cl = 9 (ddr3-1333) -1g4 C 1.87ns @ cl = 7 (ddr3-1066) -1g1 note: 1. contact micron for industrial temperature module offerings. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 11 cl = 10 cl = 9 cl = 8 cl = 7 cl = 6 cl = 5 -1g6 pc3-12800 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1g4 pc3-10600 C 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1g1 pc3-8500 C C C 1066 1066 800 667 13.125 13.125 50.625 -1g0 pc3-8500 C C C 1066 C 800 667 15 15 52.5 -80c pc3-6400 C C C C C 800 800 12.5 12.5 50 -80b pc3-6400 C C C C C 800 667 15 15 52.5 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm features pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 512mb 1gb refresh count 8k 8k row address 8k a[12:0] 16k a[13:0] device bank address 8 ba[2:0] 8 ba[2:0] device configuration 1gb 64 meg x 16 2gb 128 meg x 16 column address 1k a[9:0] 1k a[9:0] module rank address 1 s0# 1 s0# table 3: part numbers and timing parameters C 512mb modules base device: mt41j64m16, 1 1gb ddr3 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt4jtf6464az-1g6__ 512mb 64 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 mt4jtf6464az1g4__ 512mb 64 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt4jtf6464az-1g1__ 512mb 64 meg x 64 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 table 4: part numbers and timing parameters C 1gb modules base device: mt41j128m16, 1 2gb ddr3 sdram part number 2 module density configuration module bandwidth memory clock/da- ta rate clock cycles (cl- t rcd- t rp) mt4jtf12864az-1g6__ 1gb 128 meg x 64 12.8 gb/s 1.25ns/1600 mt/s 11-11-11 MT4JTF12864AZ-1G4__ 1gb 128 meg x 64 10.6 gb/s 1.5ns/1333 mt/s 9-9-9 mt4jtf12864az-1g1__ 1gb 128 meg x 64 8.5 gb/s 1.87ns/1066 mt/s 7-7-7 notes: 1. data sheets for the base device parts can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: MT4JTF12864AZ-1G4 d1. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm features pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
pin assignments and descriptions table 5: pin assignments 240-pin ddr3 udimm front 240-pin ddr3 udimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v refdq 31 dq25 61 a2 91 dq41 121 v ss 151 v ss 181 a1 211 v ss 2 v ss 32 v ss 62 v dd 92 v ss 122 dq4 152 dm3 182 v dd 212 dm5 3 dq0 33 dqs3# 63 ck1 93 dqs5# 123 dq5 153 nc 183 v dd 213 nc 4 dq1 34 dqs3 64 ck1# 94 dqs5 124 v ss 154 v ss 184 ck0 214 v ss 5 v ss 35 v ss 65 v dd 95 v ss 125 dm0 155 dq30 185 ck0# 215 dq46 6 dqs0# 36 dq26 66 v dd 96 dq42 126 nc 156 dq31 186 v dd 216 dq47 7 dqs0 37 dq27 67 v refca 97 dq43 127 v ss 157 v ss 187 nc 217 v ss 8 v ss 38 v ss 68 nc 98 v ss 128 dq6 158 nc 188 a0 218 dq52 9 dq2 39 nc 69 v dd 99 dq48 129 dq7 159 nc 189 v dd 219 dq53 10 dq3 40 nc 70 a10 100 dq49 130 v ss 160 v ss 190 ba1 220 v ss 11 v ss 41 v ss 71 ba0 101 v ss 131 dq12 161 nc 191 v dd 221 dm6 12 dq8 42 nc 72 v dd 102 dqs6# 132 dq13 162 nc 192 ras# 222 nc 13 dq9 43 nc 73 we# 103 dqs6 133 v ss 163 v ss 193 s0# 223 v ss 14 v ss 44 v ss 74 cas# 104 v ss 134 dm1 164 nc 194 v dd 224 dq54 15 dqs1# 45 nc 75 v dd 105 dq50 135 nc 165 nc 195 odt0 225 dq55 16 dqs1 46 nc 76 nc 106 dq51 136 v ss 166 v ss 196 nc/a13 1 226 v ss 17 v ss 47 v ss 77 nc 107 v ss 137 dq14 167 nc 197 v dd 227 dq60 18 dq10 48 nc 78 v dd 108 dq56 138 dq15 168 reset# 198 nc 228 dq61 19 dq11 49 nc 79 nc 109 dq57 139 v ss 169 nc 199 v ss 229 v ss 20 v ss 50 cke0 80 v ss 110 v ss 140 dq20 170 v dd 200 dq36 230 dm7 21 dq16 51 v dd 81 dq32 111 dqs7# 141 dq21 171 nc 201 dq37 231 nc 22 dq17 52 ba2 82 dq33 112 dqs7 142 v ss 172 nc 202 v ss 232 v ss 23 v ss 53 nc 83 v ss 113 v ss 143 dm2 173 v dd 203 dm4 233 dq62 24 dqs2# 54 v dd 84 dqs4# 114 dq58 144 nc 174 a12 204 nc 234 dq63 25 dqs2 55 a11 85 dqs4 115 dq59 145 v ss 175 a9 205 v ss 235 v ss 26 v ss 56 a7 86 v ss 116 v ss 146 dq22 176 v dd 206 dq38 236 v ddspd 27 dq18 57 v dd 87 dq34 117 sa0 147 dq23 177 a8 207 dq39 237 sa1 28 dq19 58 a5 88 dq35 118 scl 148 v ss 178 a6 208 v ss 238 sda 29 v ss 59 a4 89 v ss 119 sa2 149 dq28 179 v dd 209 dq44 239 v ss 30 dq24 60 v dd 90 dq40 120 v tt 150 dq29 180 a3 210 dq45 240 v tt note: 1. pin 196 is nc for 512mb and a13 for 1gb. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm pin assignments and descriptions pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions symbol type description a[13:0] input address inputs: provide the row address for activate commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the mem- ory array in the respective bank. a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 low, bank selected by ba[2:0]) or all banks (a10 high). if only one bank is to be precharged, the bank is selected by ba. a12 is also used for bc4/bl8 identification as bl on-the-fly during cas commands. the address inputs also provide the op-code during the mode register command set. a[12:0] address the 1gb ddr3 devices. a[13:0] address the 2gb ddr3 devices. ba[2:0] input bank address inputs: ba[2:0] define the device bank to which an activate, read, write, or precharge command is being applied. ba[2:0] define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ck[1:0], ck#[1:0] input clock: ck and ck# are differential clock inputs. all control, command, and address input sig- nals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. cke0 input clock enable: cke enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. dm[7:0] input data input mask: dm is an input mask signal for write data. input data is masked when dm is sampled high, along with the input data, during a write access. dm is sampled on both edges of the dqs. although the dm pins are input-only, the dm loading is designed to match that of the dq and dqs pins. odt0 input on-die termination: odt (registered high) enables termination resistance internal to the ddr3 sdram. when enabled, odt is only applied to the following pins: dq, dqs, dqs#, and dm. the odt input will be ignored if disabled via the load mode command. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: an active low cmos input referenced to v ss . the reset# input receiver is a cmos in- put defined as a rail-to-rail signal with dc high 0.8 v dd and dc low 0.2 v dd . s0# input chip select: s# enables (registered low) and disables (registered high) the command decoder. sa[2:0] input presence-detect address inputs: these pins are used to configure the temperature sensor/ spd eeprom address range on the i 2 c bus. scl input serial clock for presence-detect: scl is used to synchronize the communication to and from the temperature sensor/spd eeprom. dq[63:0] i/o data input/output: bidirectional data bus. dqs[7:0], dqs#[7:0] i/o data strobe: dqs and dqs# are differential data strobes. output with read data. edge- aligned with read data. input with write data. center-aligned with write data. sda i/o serial data: sda is a bidirectional pin used to transfer addresses and data into and out of the temperature sensor/spd eeprom on the module on the i 2 c bus. v dd supply power supply: 1.5v 0.075v. v ddspd supply serial eeprom positive power supply: +3.0v to +3.6v. the component v dd and v ddq are connected to the module vdd. v refca supply reference voltage: control, command, and address (v dd /2). v refdq supply reference voltage: dq, dm (v dd /2). v ss supply ground. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm pin assignments and descriptions pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 6: pin descriptions (continued) symbol type description v tt supply termination voltage: used for control, command, and address (v dd /2). nc C no connect: these pins are not connected on the module. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm pin assignments and descriptions pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dq map table 7: component-to-module dq map component reference number component dq module dq module pin number component reference number component dq module dq module pin number u1 0 2 9 u2 0 18 27 1 1 4 1 17 22 2 3 10 2 19 28 3 5 123 3 21 141 4 6 128 4 22 146 5 4 122 5 20 140 6 7 129 6 23 147 7 0 3 7 16 21 8 8 12 8 24 30 9 15 138 9 31 156 10 9 13 10 25 31 11 11 19 11 27 37 12 12 131 12 28 149 13 14 137 13 30 155 14 13 132 14 29 150 15 10 18 15 26 36 u3 0 34 87 u4 0 50 105 1 33 82 1 49 100 2 35 88 2 51 106 3 37 201 3 53 219 4 38 206 4 54 224 5 36 200 5 52 218 6 39 207 6 55 225 7 32 81 7 48 99 8 40 90 8 56 108 9 47 216 9 63 234 10 41 91 10 57 109 11 43 97 11 59 115 12 44 209 12 60 227 13 46 215 13 62 233 14 45 210 14 61 228 15 42 96 15 58 114 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm dq map pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 dqs1 dqs1# dm1 dqs2 dqs2# dm2 dqs3 dqs3# dm3 dqs4 dqs4# dm4 dqs5 dqs5# dm5 dqs6 dqs6# dm6 dqs7 dqs7# dm7 cs# cs# cs# cs# u1 u2 u3 u4 s0# ba[2:0] a[13/12:0] ras# cas# we# cke0 odt0 reset# ba[2:0]: ddr3 sdrams a[13/12:0]: ddr3 sdrams ras#: ddr3 sdrams cas#: ddr3 sdrams we#: ddr3 sdrams cke0: ddr3 sdrams odt0: ddr3 sdrams reset#: ddr3 sdrams ddr3 sdram x 4 ck0 ck0# ck1 ck1# a0 spd eeprom a1 a2 sa0 sa1 scl wp u6 v refca v ss ddr3 sdrams ddr3 sdrams v dd ddr3 sdrams v ddspd spd eeprom v tt ddr3 sdrams ddr3 sdrams v refdq v ss command, address and clock line terminations cke0 a[13/12:0], ras#, cas#, we#, odt, ba[2:0] dqs0 dqs0# dm0 ck0 ck0# sda dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq dqs dqs# dm dq dq dq dq dq dq dq dq ddr3 sdram v tt ddr3 sdram v dd sa2 note: 1. the zq ball on each ddr3 component is connected to an external 240 1% resistor that is tied to ground. it is used for the calibration of the components odt and output driver. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm functional block diagram pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
general description ddr3 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 8-bank ddr3 sdram devices. ddr3 sdram mod- ules use ddr architecture to achieve high-speed operation. ddr3 architecture is essentially an 8 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr3 sdram module effectively consists of a single 8 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n-bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr3 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. fly-by topology ddr3 modules use faster clock speeds than earlier ddr technologies, making signal quality more important than ever. for improved signal quality, the clock, control, com- mand, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each dram is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). inherent to fly-by topology, the timing skew between the clock and dqs signals can be easily accounted for by using the write-leveling feature of ddr3. serial presence-detect eeprom operation ddr3 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to comply with je- dec standard jc-45, appendix x: serial presence detect (spd) for ddr3 sdram modules. these bytes identify module-specific timing parameters, configuration infor- mation, and physical attributes. user-specific information can be written into the remaining 128 bytes of storage. read/write operations between the system (master) and the eeprom (slave) device occur via an i 2 c bus. write protect (wp) is connected to vss, permanently disabling hardware write protect. for further information please refer to micron technical note tn-04-42, "memory module serial presence-detect." 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm general description pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each devices data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 8: absolute maximum ratings symbol parameter min max units v dd v dd supply voltage relative to v ss C0.4 +1.975 v v in , v out voltage on any pin relative to v ss C0.4 +1.975 v table 9: operating conditions symbol parameter min nom max units notes v dd v dd supply voltage 1.425 1.5 1.575 v v refca(dc) input reference voltage command/address bus 0.49 v dd 0.5 v dd 0.51 v dd v v refdq(dc) i/o reference voltage dq bus 0.49 v dd 0.5 v dd 0.51 v dd v i vtt termination reference current from v tt C600 C +600 ma v tt termination reference voltage (dc) C com- mand/address bus 0.49 v dd - 20mv 0.5 v dd 0.51 v dd + 20mv v 1 i i input leakage current; any in- put 0v v in v dd ; v ref in- put 0v v in 0.95v (all other pins not under test = 0v) address in- puts, ras#, cas#, we#, ba, s#, cke, odt, ck, ck# C8 0 +8 a dm C2 0 +2 i oz output leakage current; 0v v out v ddq ; dq and odt are disabled; odt is high dq, dqs, dqs# C5 0 +5 a i vref v ref supply leakage current; v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) C4 0 +4 a t a module ambient operating temperature 0 C +70 c 2, 3 t c ddr3 sdram component case operating temperature 0 C +85 c 2, 3, 4 notes: 1. v tt termination voltage in excess of the stated limit will adversely affect the command and address signals voltage margin and will reduce timing margins. 2. t a and t c are simultaneous requirements. 3. for further information, refer to technical note tn-00-08: thermal applications, avail- able on microns web site. 4. the refresh rate is required to double when 85c < t c 95c. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm electrical specifications pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr3 component data sheets. component specifications are available on microns web site. module speed grades cor- relate with component speed grades, as shown below. table 10: module and component speed grades ddr3 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1g6 -125 -1g4 -15e -1g1 -187e -1g0 -187 -80c -25e -80b -25 design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the systems memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm electrical specifications pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
i dd specifications table 11: ddr3 i dd specifications and conditions C 512mb values are for the mt41j64m16 ddr3 sdram only and are computed from values specified in the 1gb (64 meg x 16) component data sheet parameter symbol 1600 1333 1066 units operating current 0: one bank activate-to-precharge i dd0 480 440 400 ma operating current 1: one bank activate-to-read-to-precharge i dd1 680 600 520 ma precharge power-down current: slow exit i dd2p 48 48 48 ma precharge power-down current: fast exit i dd2p 180 160 140 ma precharge quiet standby current i dd2q 268 240 212 ma precharge standby current i dd2n 280 260 220 ma precharge standby odt current i dd2nt 460 420 380 ma active power-down current i dd3p 180 160 140 ma active standby current i dd3n 260 240 220 ma burst read operating current i dd4r 1280 1160 1040 ma burst write operating current i dd4w 1720 1420 1180 ma refresh current i dd5b 1040 960 880 ma self refresh temperature current: max t c = 85c i dd6 24 24 24 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et 36 36 36 ma all banks interleaved read current i dd7 1840 1680 1520 ma reset current i dd8 56 56 56 ma table 12: ddr3 i dd specifications and conditions C 1gb values are for the mt41j128m16ddr3 sdram only and are computed from values specified in the 2gb (128 meg x 16) component data sheet (die rev d) parameter symbol 1600 1333 1066 units operating current 0: one bank activate-to-precharge i dd0 tbd 480 420 ma operating current 1: one bank activate-to-read-to-precharge i dd1 tbd 600 520 ma precharge power-down current: slow exit i dd2p tbd 48 48 ma precharge power-down current: fast exit i dd2p tbd 140 120 ma precharge quiet standby current i dd2q tbd 260 220 ma precharge standby current i dd2n tbd 260 220 ma precharge standby odt current i dd2nt tbd 400 360 ma active power-down current i dd3p tbd 180 160 ma active standby current i dd3n tbd 300 240 ma burst read operating current i dd4r tbd 1160 980 ma burst write operating current i dd4w tbd 1340 1120 ma refresh current i dd5b tbd 1020 980 ma self refresh temperature current: max t c = 85c i dd6 tbd 36 36 ma self refresh temperature current (srt-enabled): max t c = 95c i dd6et tbd 48 48 ma 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm electrical specifications pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
table 12: ddr3 i dd specifications and conditions C 1gb (continued) values are for the mt41j128m16ddr3 sdram only and are computed from values specified in the 2gb (128 meg x 16) component data sheet (die rev d) parameter symbol 1600 1333 1066 units all banks interleaved read current i dd7 tbd 1780 1560 ma reset current i dd8 tbd 56 56 ma 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm electrical specifications pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
serial presence-detect eeprom table 13: serial presence-detect eeprom dc operating conditions all voltages referenced to v ddspd parameter/condition symbol min max units supply voltage v ddspd 3.0 3.6 v input low voltage: logic 0; all inputs v il C0.6 v ddspd + 0.3 v input high voltage: logic 1; all inputs v ih v ddspd + 0.7 v ddspd + 1.0 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 2.0 a output leakage current: v out = gnd to v dd i lo 0.05 2.0 a table 14: serial presence-detect eeprom ac operating conditions parameter/condition symbol min max units notes clock frequency t scl 10 400 khz clock pulse width high time t high 0.6 C s clock pulse width low time t low 1.3 C s sda rise time t r C 300 s 1 sda fall time t f 20 300 ns 1 data-in setup time t su:dat 100 C ns data-in hold time t hd:di 0 C s data-out hold time t hd:dat 200 900 ns data out access time from scl low t aa:dat 0.2 0.9 s 2 start condition setup time t su:sta 0.6 C s 3 start condition hold time t hd:sta 0.6 C s stop condition setup time t su:sto 0.6 C s time the bus must be free before a new transition can start t buf 1.3 C s write time t w C 10 ms notes: 1. guaranteed by design and characterization, not necessarily tested. 2. to avoid spurious start and stop conditions, a minimum delay is placed between the fall- ing edge of scl and the falling or rising edge of sda. 3. for a restart condition, or following a write cycle. serial presence-detect data for the latest serial presence-detect data, refer to micron's spd page: www.micron.com/spd . 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm serial presence-detect eeprom pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.
module dimensions figure 3: 240-pin ddr3 udimm 30.50 (1.20) 29.85 (1.175) pin 1 17.3 (0.68) typ 2.50 (0.098) d (2x) 2.30 (0.091) typ 5.0 (0.197) typ 123.0 (4.84) typ 1.0 (0.039) typ 0.80 (0.031) typ 0.75 (0.03) r (8x) 0.76 (0.030) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 47.0 (1.85) typ 71.0 (2.79) typ 9.5 (0.374) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 2.70 (0.106) max 2.20 (0.087) typ 1.45 (0.057) typ 3.05 (0.12) typ 54.68 (2.15) typ 3.0 (0.118) x4 typ u1 u2 u3 u4 u6 no components this side of module 45 (4x) notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 512mb, 1gb (x64, sr) 240-pin ddr3 sdram udimm module dimensions pdf: 09005aef83cad6ed jtf4c64_128x64az.pdf C rev. a 10/09 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2009 micron technology, inc. all rights reserved.

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